In the past there has not been much concern with regards to maintaining signal edge rates (or slew rates) on busses. This is because there were little negative effects of having variable slew rates on slower speed busses. However as bus speeds increase, there are tighter restrictions on edge rates [volts/nanoseconds] of a signal switching high to low, or vice versa. If the slew rate is faster or slower, there could potentially be problems with signal integrity and transmissions. Thus, there are tight timing windows for signal transitions on the current high-speed busses.
Currently, the hardware design for integrated circuits are manually simulated and are deduced from a mechanism indicating process voltage and temperature (PVT) to determine the slew rate of the signals being transmitted on a high-speed bus. However if a mechanism indicating (PVT) is malfunctioning, it is impossible to determine slew rate.